The present invention relates to testing of semiconductor memory devices, such as dynamic random access memory devices, and in particular, the invention relates to a method and circuit for rapidly equilibrating paired digit lines of a memory array of a semiconductor memory device during testing using spare rows of the memory array.
Semiconductor memory devices, such as dynamic random access memory (DRAM) devices, undergo a tremendous amount of testing at various steps in the production process. Typically, DRAM devices are tested by using write and read operations to determine whether all of the cells of the memory array can properly store data signals and whether the stored data signals can be read out of the memory array. As memory chips become more dense, the testing time that is required to verify that data is being correctly stored and read out has increased dramatically.
In one test that is commonly used to identify faulty cells of a memory array, a signal having a logic level of either one or zero is applied to one group of the memory cells and signals of the opposite logic level are applied to the remaining cells. The logic level signals are then read out of the cells individually and tested for the correct logic levels. This test must be repeated for each of the cells in the memory array and the entire procedure is repeated with signals of the opposite logic levels.
Prior to any memory access cycle, both for normal operation of the memory and during testing of the memory, paired digit lines must be equilibrated to a common potential, typically one-half the supply voltage Vcc. Memory devices include equilibration circuits for this purpose. Typically, the equilibration circuit comprises one or more transistors that are connected between the digit lines that form a pair of paired digit lines. These transistors are enabled by an equilibrate enable signal that is provided prior to the start of a memory access cycle. When enabled, the transistors short the paired digit lines together. The equilibrating voltage is applied to these transistors which transfer the voltage to the interconnected digit lines.
Conventionally, the equilibrating voltage is applied to the transistors of the equilibration circuit through a xe2x80x9clongxe2x80x9d transistor which functions as a bleeder resistance in the case of a row-to-column short for the memory. However, the presence of this large resistance in the application path for the equilibrating voltage decreases the rate at which the digit lines can be equilibrated to the final generator voltage. Typically, digit line equilibration can take 40 to 50 microseconds, and as long as 100 microseconds, depending on what the final generator voltage is, for each memory row being tested. Consequently, testing an array of memory cells requires a substantial amount of time, and the time required to pre-charge the digit lines in each row significantly impacts the cost of testing of the memory device.
The time required for testing DRAM devices can be reduced by using a test procedure that is commonly referred to as xe2x80x9carray hoppingxe2x80x9d. In this procedure, digit line equilibration is initiated in a first portion of the array and, during equilibration of the first portion of the array, the test procedure is advanced to a second portion of the array in which the memory cells have already been equilibrated. The first portion of the array is tested after a time delay that is sufficient to achieve the digit line equilibration desired. Although xe2x80x9carray hoppingxe2x80x9d provides a reduction in the total time required for testing of a semiconductor memory, typically only four xe2x80x9chopsxe2x80x9d are practical, thus limiting the test time reduction that can be achieved for testing the complete memory array.
For the reasons stated above, and for other reasons which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a method and circuit for rapidly equilibrating paired digit lines of a semiconductor memory device, such as a random access memory device, during testing to minimize the time that is required for conducting the testing of the memory device.
The present invention provides a circuit fabricated in an integrated circuit memory device for equilibrating paired digit lines of a memory array of the memory device. The circuit includes pass circuitry interposed between the paired digit lines and a source of an equilibrating voltage for connecting the equilibrating voltage to the paired digit lines. The pass circuitry includes a plurality of pass gates disposed in at least one spare row of the memory array and coupled to a further word line for the one spare row of the memory array. A drive circuit produces a drive signal for activating the word line for the spare row, for enabling the pass gates to connect the equilibrating voltage to the paired digit lines.
In accordance with another aspect of the invention, there is provided an integrated circuit memory device including a memory array including a plurality of memory cells arranged to form a matrix of rows and columns, a plurality of row lines for accessing the memory cells and a plurality of paired digit lines coupled to the memory array. A test mode circuit is provided for operating the memory device in a test mode. The memory device includes conventional equilibration circuitry connected between first and second digit lines of at least one of the paired digit lines for applying an equilibrating voltage to the first and second digit lines and for equilibrating the potentials on the first and second digit lines. The memory device further includes pass circuitry connected between first and second digit lines and the source of the equilibration voltage, in parallel with the equilibration circuitry, for coupling the equilibration voltage directly to the digit lines. In one embodiment, the memory device includes a drive circuit for enabling the pass circuitry when the memory device is being operated in the test mode, for bypassing the conventional equilibration circuitry to rapidly equilibrate the digit lines to the equilibration voltage.
In accordance with a further aspect of the invention, there is provided a method for equilibrating paired digit lines of an integrated circuit memory device during the testing of the memory device. The method includes enabling the memory device to operate in a test mode, enabling equilibration circuitry for applying an equilibrating voltage to the paired digit lines during an equilibration cycle, and for equilibrating the potentials on the digit lines of each digit line pair prior to the start of each memory access cycle, and providing a bypass path around at least a portion of the equilibration circuitry during at least a portion of the equilibration cycle for connecting the equilibrating voltage directly to digit lines of each digit line. In one embodiment, the bypass path is provided by enabling a plurality of pass gates prior to the start of a memory access cycle.